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sgls219a ? november 2003 ? revised may 2008 8 features qualified for automotive applications operating input voltage 8 v to 40 v input voltage feed-forward compensation < 1 % internal 0.7-v reference programmable fixed-frequency up to 1 mhz voltage mode controller internal gate drive outputs for high-side and synchronous n-channel mosfets 16-pin powerpad package ( jc = 2 c/w) thermal shutdown externally synchronizable programmable high-side current limit programmable closed-loop soft-start tps40050 source only tps40051 source/sink tps40053 source/sink with v out prebias applications power modules networking/telecom industrial servers description the tps4005x is a family of high-voltage, wide input (8 v to 40 v), synchronous, step-down converters. the tps4005x family offers design flexibility with a variety of user programmable functions, including soft-start, uvlo, operating frequency, voltage feed- forward, high-side current limit, and loop compensation. the tps4005x are also synchronizable to an external supply. they incorporate mosfet gate drivers for external n-channel high-side and synchronous rectifier (sr) mosfets. gate drive logic incorporates anti-cross conduction circuitry to prevent simultaneous high-side and synchronous rectifier conduction. the tps4005x uses voltage feed-forward control techniques to provide good line regulation over the wide (4:1) input voltage range, and fast response to input line transients with near constant gain with input variation which eases loop compensation. the externally programmable current limit provides pulse-by-pulse current limit, as well as hiccup mode operation utilizing an internal fault counter for longer duration overloads. ordering information ? t a application package ? part number source ? plastic htssop (pwp) tps40050qpwprq1 ?40 c to 125 c source/sink ? plastic htssop (pwp) tps40051qpwprq1 ?40 c to 125 c source/sink ? with prebias plastic htssop (pwp) tps40053qpwprq1 ? for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at http://www.ti.com. ? package drawings, thermal data, and symbolization are available at http://www .ti.com/packaging. this pwp package is taped and reeled as indicated by the r suffix on the device type (i.e., tps40050qpwprq1). see the applicati on section of the data sheet for powerpad drawing and layout information. ? see application information section, pg. 8 powerpad is trademark of texas instruments. please be aware that an important notice concerning availability , standard warranty, and use in critical applications of t exas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com copyright ? 2008 texas instruments incorporated
sgls219a ? november 2003 ? revised may 2008 www.ti.com 2 these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam duri ng storage or handling to prevent electrostatic damage to the mos gates. simplified application udg?02130 5 13 12 16 15 1 2 3 kff rt bp5 sgnd vin hdrv sw bp10 4 sync 11 ilim tps40050qpwp 6 ss/sd 7 vfb 8 comp 14 boost ldrv 10 pgnd 9 + ? v in v out absolute maximum ratings over operating f ree-air temperature range unless otherwise noted (3) tps40050-q1 tps40051-q1 TPS40053-Q1 unit vin 45 input voltage range, vi vfb, kff, ss, sync ?0.3 to 6 input voltage range, vi sw ?0.3 to 45 v sw, transient < 50 ns ?2.5 v output voltage range, v o comp, kff, rt, ss ?0.3 to 6 output current, i out rt 200 a operating junction temperature range, t j ?40 to 140 storage temperature, t stg ?55 to 150 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c (3) stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating con ditions? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions min nom max unit input voltage, v i 8 40 v operating free-air temperature, t a ?40 125 c
sgls219a ? november 2003 ? revised may 2008 www.ti.com 3 thermal pad 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 kff rt bp5 sync sgnd ss/sd vfb comp ilim vin boost hdrv sw bp10 ldrv pgnd pwp p ackage (4)(5) (top view) (4) for more information on the pwp package, refer to ti technical brief, literature no. slma002. (5) powerpad heat slug must be connected to sgnd (pin 5) or electrically isolated from all other pins.
sgls219a ? november 2003 ? revised may 2008 www.ti.com 4 electrical characteristics t a = ?40 c to 125 c, v in = 24 v dc , r t = 90.9 k ? , i kff = 150 a, f sw = 500 khz, all parameters at zero power dissipation (unless otherwise noted) parameter test conditions min typ max unit input supply v in input voltage range, vin 8 40 v operating current i dd quiescent current output drivers not switching, v fb 0.75 v 1.5 3.0 ma bp5 v bp5 output voltage i out 1 ma 4.7 5.0 5.2 v oscillator/ramp generator (2) f osc accuracy 8 v v in 40 v 470 500 550 khz v ramp pwm ramp voltage (1) v peak ?v val 2.0 v v ih high-level input voltage, sync 2 5 v v il low-level input voltage, sync 0.8 2 v i sync input current, sync 5 10 a pulse width, sync 50 ns v rt rt voltage 2.38 2.50 2.58 v maximum duty cycle v fb = 0 v, f sw 500 khz 85% 94% maximum duty cycle v fb = 0 v, 500 khz f sw 1 mhz 80% minumum duty cycle v fb 0.75 v 0% v kff feed-forward voltage 3.35 3.48 3.65 v i kff feed-forward current operating range (1) 20 1100 a soft start i ss soft-start source current 1.4 2.35 3 a v ss soft-start clamp voltage 2.7 3.7 4.7 v t dsch discharge time c ss = 220 pf 1.5 2.2 2.9 s t ss soft-start time c ss = 220 pf, 0 v v ss 1.6 v 110 155 210 s bp10 v bp10 ouput voltage i out 1 ma 9.0 9.6 10.3 v error amplifier 8 v v in 40 v, t a = 25 c 0.698 0.700 0.704 v fb feedback input voltage 8 v v in 40 v, 0 c t a 85 c 0.690 0.700 0.707 v v fb feedback input voltage 8 v v in 40 v, ?40 c t a 125 c 0.650 0.700 0.750 v g bw gain bandwidth 3.0 5.0 mhz a vol open loop gain 60 80 db i oh high-level output source current 2.0 4.0 ma i ol low-level output sink current 2.5 4.0 ma v oh high-level output voltage i source = 500 a 3.2 3.5 v v ol low-level output voltage i sink = 500 a 0.20 0.35 v i bias input bias current v fb = 0.7 v ?200 100 200 na (1) ensured by design. not production tested. (2) i kff increases with sync frequency, i kff decreases with maximum duty cycle
sgls219a ? november 2003 ? revised may 2008 www.ti.com 5 electrical characteristics t a = ?40 c to 125 c, v in = 24 v dc , r t = 90.9 k ? , i kff = 150 a, f sw = 500 khz, all parameters at zero power dissipation (unless otherwise noted) parameter test conditions min typ max unit current limit i sink current limit sink current 6.2 10.0 13 a propagation delay to output v ilim = 23.7 v, v sw = (v ilim ? 0.5 v) 200 300 500 propagation delay to output v ilim = 23.7 v, v sw = (v ilim ? 2 v) 100 200 400 ns t on switch leading-edge blanking pulse time (1) 100 ns t off off time during a fault 7 cycles v ilim = 23.6 v, t a = 25 c ?125 ?35 v os offset voltage sw vs. ilim v ilim = 23.6 v, 0 c t a 85 c ?140 ?75 ?15 mv v os offset voltage sw vs. ilim v ilim = 23.6 v, ?40 c t a 125 c ?250 10 mv output driver t lrise low-side driver rise time c load = 2200 pf 48 96 t lfall low-side driver fall time c load = 2200 pf 24 48 ns t hrise high-side driver rise time c load = 2200 pf, (hdrv ? sw) 48 96 ns t hfall high-side driver fall time c load = 2200 pf, (hdrv ? sw) 36 72 v oh high-level ouput voltage, hdrv i hdrv = ?0.1 a (hdrv ? sw) boost ?1.5 v boost ?1.0 v v ol low-level ouput voltage, hdrv i hdrv = 0.1 a (hdrv ? sw) 0.75 v v oh high-level ouput voltage, ldrv i ldrv = ?0.1 a bp10 ?1.4 v bp10 ? 1.0 v v v ol low-level ouput voltage, ldrv i ldrv = 0.1 a 0.5 minimum controllable pulse width 100 150 ns ss/sd shutdown v sd shutdown threshold voltage outputs off 90 125 150 mv v en device active threshold voltage 190 210 245 mv boost regulator v boost output voltage v in = 24.0 v 31.5 32.5 33.5 v rectifier zero current com parator (tps40050/tps40053 ss only) v sw switch voltage ldrv output off ?10 ?0.5 10 mv sw node i leak leakage current (1) 25 a thermal shutdown t sd shutdown temperature (1) 165 c t sd hysteresis (1) 20 c uvlo v uvlo kff programmable threshold voltage r kff = 28.7 k ? 6.9 7.5 7.9 v (1) ensured by design. not production tested. (2) i kff increases with sync frequency, i kff decreases with maximum duty cycle
sgls219a ? november 2003 ? revised may 2008 www.ti.com 6 terminal functions terminal i/o description name no. i/o description boost 14 o gate drive voltage for the high side n-channel mosfet. the boost voltage is 9 v greater than the input voltage. a 0.1- f ceramic capacitor should be connected from this pin to the drain of the lower mosfet. bp5 3 o 5-v reference. this pin should be bypassed to ground with a 0.1- f ceramic capacitor. this pin may be used with an external dc load of 1 ma or less. bp10 11 o 10-v reference used for gate drive of the n-channel synchronous rectifier . this pin should be bypassed by a 1- f ceramic capacitor. this pin may be used with an external dc load of 1 ma or less. comp 8 o output of the error amplifier, input to the pwm comparat or. a feedback network is connected from this pin to the vfb pin to compensate the overall loop. the comp pin is internally clamped above the peak of the ramp to improve large signal transient response. hdrv 13 o floating gate drive for the high-side n-channel mosfet. this pin switches from boost (mosfet on) to sw (mosfet off). ilim 16 i current limit pin, used to set the overcurrent threshold. an internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to vcc. the voltage on this pin is compared to the voltage drop (vin ?sw) across the high side mosfet during conduction. kff 1 i a resistor is connected from this pin to vin to program the amount of voltage feed-forward. the current fed into this pin is internally divided and used to control the slope of the pwm ramp. ldrv 10 o gate drive for the n-channel synchronous rectifier. this pin switches from bp10 (mosfet on) to ground (mosfet off). pgnd 9 ? power ground reference for the device. there should be a low-impedance path from this pin to the source(s) of the lower mosfet(s). rt 2 i a resistor is connected from this pin to ground to set the internal oscillator and switching frequency. sgnd 5 ? signal ground reference for the device. ss/sd 6 i soft-start programming pin. a capacitor connected from this pin to ground programs the soft-start time. the capacitor is charged with an internal current source of 2.3 a. the resulting voltage ramp on the ss pin is used as a second non-inverting input to the error amplifier. output voltage regulation is controlled by the ss voltage ramp until the voltage on the ss pin reaches the internal reference voltage of 0.7 v. pulling this pin low disables the controller. sw 12 i this pin is connected to the switched node of the converter and used for overcurrent sensing. the tps40050 and tps40053 versions use this pin for zero current sensing as well. sync 4 i syncronization input for the device. this pin can be used to synchronize the oscillator to an external master frequency. if synchronization is not used, connect this pin to sgnd. vfb 7 i inverting input to the error amplifier. in normal operation the voltage on this pin is equal to the internal reference voltage, 0.7 v. vin 15 i supply voltage for the device.
sgls219a ? november 2003 ? revised may 2008 www.ti.com 7 simplified block diagram udg?02128 1 2 7 + + 6 t start 0v7ref soft start ramp generator clk oscillator 13 10 14 n?channel driver 12 9 11 15 8 4 5 bp10 bp10 07vref 7 7 16 3?bit up/down fault counter 7 7 7 07vref 1v5ref 3v5ref reference voltages 7 fault 7 restart clk 7 clk 7 bp5 3 7 bp5 7 restart + 07vref 7 7 7 fault cl sq q r 7 clk cl sw 7 sw sq q r 7 hdrv ldrv pgnd boost bp10 vin sync rt kff bp5 vfb ss/sd comp ilim sgnd zero current detector (tps40050 only) n?channel driver 10v regulator + ? 7 1v5ref
sgls219a ? november 2003 ? revised may 2008 www.ti.com 8 application information the tps40050/51/53 family of parts allows the user to optimize the pwm controller to the specific application. the tps40051 will be the controller of choice for synchronous buck designs which will include most applications. it has two quadrant operation and will source or sink output current. this provides the best transient response. the tps40050 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. this controller also emulates a standard buck converter at light loads where the inductor current goes discontinuous. at continuous output inductor currents the controller operates as a synchronous buck converter to optimize efficiency. the tps40053 operates in one quadrant as a standard buck converter during start up. after the output has reached the regulation point, the controller operates in two quadrant mode and is put in a synchronous buck configuration. this is useful for applications that have the output voltage ?pre-biased? at some voltage before the controller is enabled. when the tps40053 controller is enabled it does not sink current during start up which would pull current from the pre-biased voltage supply. sw node resistor and diode the sw node of the converter is negative during the dead time when both the upper and lower mosfets are off. the magnitude of this negative voltage is dependent on the lower mosfet body diode and the output current which flows during this dead time. this negative voltage could affect the operation of the controller, especially at low input voltages. therefore, a resistor (between 3.3 ? and 4.7 ? ) and schottky diode must be placed between the lower mosfet drain and pin 12, sw, of the controller as shown in figure 15. the schottky diode must have a voltage rating to accommodate the input voltage and ringing on the sw node of the converter. a 30-v schottky such as a bat54 or a 40-v schottky such as a zetex zhcs400 or vishay sd103aws are adequate. these components are shown in figure 15 as r sw and d2. setting the switching frequency (programming the clock oscillator) the tps4005x has independent clock oscillator and ramp generator circuits. the clock oscillator serves as the master clock to the ramp generator circuit. the switching frequency, f sw in khz, of the clock oscillator is set by a single resistor (r t ) to ground. the clock frequency is related to r t , in k ? by equation (1) and the relationship is charted in figure 2. r t 1 f sw 17.82 10 6 23 k (1)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 9 application information programming the ramp generator circuit the ramp generator circuit provides the actual ramp used by the pwm comparator. the ramp generator provides voltage feed-forward control by varying the pwm ramp slope with line voltage, while maintaining a constant ramp magnitude. varying the pwm ramp directly with line voltage provides excellent response to line variations since the pwm does not have to wait for loop delays before changing the duty cycle. (see figure 1). ramp comp sw vin udg?02131 vin sw comp ramp v peak v valley t 2 t on1 > t on2 and d 1 > d 2 t on2 t on1 d t on t t 1 figure 1. voltage feed-forward effect on pwm duty cycle the pwm ramp must be faster than the master clock frequency or the pwm is prevented from starting. the pwm ramp time is programmed via a single resistor (r kff ) pulled up to vin. r kff is related to r t , and the minimum input voltage, v in(min) through the following: r kff v in (min) 3.5 58.14 r t 1340 where: v in(min) is the ensured minimum start-up voltage. the actual start-up voltage is nominally about 10% lower at 25 c. r t is the timing resistance in k ? the curve showing the r kff required for a given switching frequency, f sw , is shown in figure 3. (2)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 10 figure 2 f sw ? switching frequency ? khz switching frequency vs timing resistance 0 100 0 200 400 600 800 100 0 200 300 400 500 600 r t ? timing resistance ? k ? 100 0 200 300 400 500 600 200 400 600 800 100 0 100 700 300 500 700 900 feed-forward impedance vs switching frequency r kff ? feed-forward impedance ? k ? figure 3 f sw ? switching frequency ? khz v in = 25 v v in = 15 v v in = 9 v uvlo operation the tps4005x uses variable (user programmable) uvlo protection. the uvlo circuit holds the soft-start low until the input voltage has exceeded the user programmable undervoltage threshold. the tps4005x uses the feed-forward pin, kff, as a user programmable low-line uvlo detection. this variable low-line uvlo threshold compares the pwm ramp duration to the oscillator clock period. an undervoltage condition exists if the tps4005x receives a clock pulse before the ramp has reached 90% of its full amplitude. the ramp duration is a function of the ramp slope, which is directly related to the current into the kff pin. the kff current is a function of the input voltage and the resistance from kff to the input voltage. the kff resistor can be referenced to the oscillator frequency as descibed in equation (3): r kff v in (min) 3.5 58.14 r t 1340 where:. v in is the desired start-up (uvlo) input voltage r t is the timing resistance in k ? the variable uvlo function uses a three?bit full adder to prevent spurious shut-downs or turn-ons due to spikes or fast line transients. when the adder reaches a total of seven counts in which the ramp duration is shorter than the clock cycle a powergood signal is asserted and a soft-start initiated, and the upper and lower mosfets are turned off. (3)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 11 application information once the soft-start is initiated, the uvlo cicruit must see a total count of seven cycles in which the ramp duration is longer than the clock cycle before an undervoltage condition is declared. (see figure 4). udg?02132 clock pwm ramp powergood vin uvlo threshold 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 figure 4. undervoltage lockout operation some applications may require an additional circuit to prevent false restarts at the uvlo voltage level. this applies to applications which have high impedance on the input voltage line or which have excessive ringing on the v in line. the input voltage impedance can cause the input voltage to sag enough at start-up to cause a uvlo shutdown and subsequent restart. excessive ringing can also affect the voltage seen by the device and cause a uvlo shutdown and restart. a simple external circuit provides a selectable amount of hysteresis to prevent the nuisance uvlo shutdown. assuming a hysteresis current of 10% i kff , and the peak detector charges to 8 v and v in(min) = 18 v, the value of r a is calculated by: r a r kff ( 8 3.5 ) 0.1 v in(min) 3.5 565 k 562 k c a is chosen to maintain the peak voltage between switching cycles. to keep the capacitor charge from drooping 0.1-v, or from 8 v to 7.9 v. c a ( 8 3.5 ) r a 7.9 f sw the value of c a imay calculate to less than 10 pf, but some standard value up to 470 pf works adequately. the diode can be a small signal switching diode or schottky rated for more then 20 v. figure 5 illustrates a typical implementation using a small switching diode. the tolerance on the uvlo set point also affects the maximum duty cycle achievable. if the uvlo starts the device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at the nominal start up voltage. (4) (5)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 12 application information udg?03034 d a c a 470 pf r a 562 k r kff 182 k 1 2 3 4 16 15 14 13 ilim vin boost hdrv kff rt bp5 sync tps40050pwp tps40051pwp 5 6 7 8 12 11 10 9 sw bp10 ldrv pgnd sgnd ss vfb comp vin + ? pwp 1n914, 1n4150 type signal diode figure 5. hysteresis for programmable uvlo bp5 and bp10 internal voltage regulators start-up characteristics of the bp5 and bp10 regulators over different temperature ranges are shown in figures 6 and 7. slight variations in the bp5 occurs dependent upon the switching frequency. variation in the bp10 regulation characteristics is also based on the load presented by switching the external mosfets. 28 46 12 10 1 2 3 4 5 6 input voltage vs bp5 voltage 25 c 110 c ?55 c figure 6. v in ? input voltage ? v v bp5 ? bp5 voltage ? v 28 46 12 10 0 2 4 6 8 10 input voltage vs bp10 voltage figure 7. v in ? input voltage ? v v bp10 ? bp10 voltage ? v ?55 c 110 c 25 c
sgls219a ? november 2003 ? revised may 2008 www.ti.com 13 application information selecting the inductor value the inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. too large an inductance results in lower ripple current but is physically larger for the same load current. too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. a good compromise is to select the inductance value such that the converter doesn?t enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. the inductance value is described in equation (6). l v in v o v o v in i f sw (henries) where:. v o is the output voltage ? i is the peak-to-peak inductor current calculating the output capacitance the output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any output voltage deviation requirement during a load transient. the output ripple voltage is a function of both the output capacitance and capacitor esr. the worst case output ripple is described in equation (7). v i esr 1 8 c o f sw v p p the output ripple voltage is typically between 90% and 95% due to the esr component. the output capacitance requirement typically increases in the presence of a load transient requirement. during a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. the amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the inductor. stepping the load from a heavy load to a light load results in an output overshoot. excess energy stored in the inductor must be absorbed by the output capacitance. the energy stored in the inductor is described in equation (8). e l 1 2 l i 2 (joules) where: i 2 i oh 2 i ol 2 ( amperes ) 2 where: i oh is the output current under heavy load conditions i ol is the output current under light load conditions (6) (7) (8) (9)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 14 application information energy in the capacitor is described in equation (10). e c 1 2 c v 2 (joules) where: v 2 v f 2 v i 2 volts 2 where: v f is the final peak capacitor voltage v i is the initial capacitor voltage substituting equation (9) into equation (8), then substituting equation (11) into equation (10), then setting equation (10) equal to equation (8), and then solving for c o yields the capacitance described in equation (12). c o l i oh 2 i ol 2 v f 2 v i 2 (farads) programming soft start tps4005x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. soft-start is programmed by charging an external capacitor (c ss ) via an internally generated current source. the voltage on c ss is fed into a separate non-inverting input to the error amplifier (in addition to fb and 0.7-v vref). the loop is closed on the lower of the c ss voltage or the internal reference voltage ( 0.7-v vref). once the c ss voltage rises above the internal reference voltage, regulation is based on the internal reference. to ensure a controlled ramp-up of the output voltage the soft-start time should be greater than the l-c o time constant as described in equation (13). t start
2 l c o (seconds) there is a direct correlation between t start and the input current required during start-up. the faster t start , the higher the input current required during start-up. this relationship is describe in more detail in the section titled, programming the current limit which follows. the soft-start capacitance, c ss , is described in equation (14). for applications in which the v in supply ramps up slowly, (typically between 50 ms and 100 ms) it may be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance uvlo tripping. the soft-start time should be longer than the time that the v in supply transitions between 6 v and 7 v. c ss 2.3 a 0.7 v t start (farads) (10) (11) (12) (13) (14)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 15 application information programming current limit the tps4005x uses a two-tier approach for overcurrent protection. the first tier is a pulse-by-pulse protection scheme. current limit is implemented on the high-side mosfet by sensing the voltage drop across the mosfet when the gate is driven high. the mosfet voltage is compared to the voltage dropped across a resistor connected from vin pin to the ilim pin when driven by a constant current sink. if the voltage drop across the mosfet exceeds the voltage drop across the ilim resistor, the switching pulse is immediately terminated. the mosfet remains off until the next switching cycle is initiated. the second tier consists of a fault counter. the fault counter is incremented on an overcurrent pulse and decremented on a clock cycle without an overcurrent pulse. when the counter reaches seven (7) a restart is issued and seven soft-start cycles are initiated. both the upper and lower mosfets are turned off during this period. the counter is decremented on each soft-start cycle. when the counter is decremented to zero, the pwm is re-enabled. if the fault has been removed the output starts up normally. if the output is still present the counter counts seven overcurrent pulses and re-enters the second-tier fault mode. see figure 6 for typical overcurrent protection waveforms. the minimum current limit setpoint (i lim ) depends on t start , c o , v o , and the load current at turn-on (i l ). i lim c o v o t start i l (amperes) the current limit programming resistor (r ilim ) is calculated using equation (16). r ilim i oc r ds(on)[max] 1.12 i sink v os i sink ( ) where: i sink is the current into the ilim pin and is nominally 10 a, i oc is the overcurrent setpoint which is the dc output current plus one-half of the peak inductor current v os is the overcurrent comparator offset and is nominally ?75 mv udg?02136 hdrv clock v vin ?v sw ss 7 current limit trips (hdrv cycle terminated by current limit trip) 7 soft-start cycles v ilim t blanking figure 8. typical current limit protection waveforms (15) (16)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 16 application information synchronizing to an external supply the tps4005x can be synchronized to an external clock through the sync pin. the synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. the clock frequency at the sync pin replaces the master clock generated by the oscillator circuit. pulling the sync pin low programs the tps4005x to freely run at the frequency programmed by r t . the higher synchronization must be factored in when programming the pwm ramp generator circuit. if the pwm ramp is interrupted by the sync pulse, a uvlo condition is declared and the pwm becomes disabled. t ypically this is of concern under low-line conditions only. in any case, r kff needs to be adjusted for the higher switching frequency. in order to specify the correct value for rkff at the synchronizing frequency, calculate a ?dummy? value for rt that would cause the oscillator to run at the synchronizing frequency. do not use this value of rt in the design. r t(dummy) 1 f sync 10 6 23 k use the value of r t(dummy) to calculate the value for r kff . r kff v in(min) 3.5 v 58.14 r t(dummy) 1340 k this value of r kff ensures that uvlo is not engaged when operating at the synchronization frequency. loop compensation voltage-mode buck-type converters are typically compensated using type iii networks. since the tps4005x uses voltage feedforward control, the gain of the pwm modulator with voltage feedforward circuit must be included. the modulator gain is described in figure 9, with v in being the minimum input voltage required to cause the ramp excursion to cover the entire switching period as described in equation (19). a mod v in v s or a mod(db) 20 log v in v s duty dycle, d, varies from 0 to 1 as the control voltage, v c , varies from the minimum ramp voltage to the maximum ramp voltage, v s . also, for a synchronous buck converter, d = v o / v in . to get the control voltage to output voltage modulator gain in terms of the input voltage and ramp voltage, d v o v in v c v s or v o v c v in v s (17) (18) (19) (20)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 17 application information calculate the poles and zeros for a buck converter using voltage mode control there is a double pole due to the output l-c o . the double pole is located at the frequency calculated in equation (21). f lc 1 2 l c o (hertz) there is also a zero created by the output capacitance, c o , and its associated esr. the esr zero is located at the frequency calculated in equation (22). f z 1 2 esr c o (hertz) calculate the value of r bias to set the output voltage, v out . r bias 0.7 r1 v out 0.7 the maximum crossover frequency (0 db loop gain) is calculated in equation (24). f c f sw 4 (hertz) typically, f c is selected to be close to the midpoint between the l-c o double pole and the esr zero. at this frequency, the control to output gain has a ?2 slope (?40 db/decade), while the type iii topology has a +1 slope (20 db/decade), resulting in an overall closed loop ?1 slope (?20 db/decade). figure 10 shows the modulator gain, l-c filter, output capacitor esr zero, and the resulting response to be compensated. figure 9 v c pwm modulator relationships v s d = v c / v s modulator gain vs switching frequency modulator gain ? db figure 10 f sw ? switching frequency ? hz 100 1 k 10 k 100 k esr zero, + 1 lc filter, ? 2 a mod = v in / v s resultant, ? 1 (21) (22) (23) (24)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 18 a pplication information a type iii topology, shown in figure 11, has two zero-pole pairs in addition to a pole at the origin. the gain and phase boost of a t ype iii topology is shown in figure 12. the two zeros are used to compensate the l-c o double pole and provide phase boost. the double pole is used to compensate for the esr zero and provide controlled gain roll-off. in many cases the second pole can be eliminated and the amplifier?s gain roll-off used to roll-off the overall gain at higher frequencies. r bias figure 11. type iii compensation configuration udg?0218 9 + r1 r3 c3 c2 (optional) c1 r2 7 8 vref vout comp vfb figure 12. type iii compensation gain and phase gain 180 ?90 ?270 phase + 1 ? 1 ? 1 0 db the poles and zeros for a type iii network are described in equations (25). f z1 1 2 r2 c1 (hertz) f z2 1 2 r1 c3 (hertz) f p1 1 2 r2 c2 (hertz) f p2 1 2 r3 c3 (hertz) the value of r1 is somewhat arbitraty, but influences other component values. a value between 50k ? and 100k ? usually yields reasonable values. the unity gain frequency is described in equation (26) f c 1 2 r1 c2 g (hertz) where g is the reciprocal of the modulator gain at f c . the modulator gain as a function of frequency at f c , is described in equation (27). amod(f) amod f lc f c 2 and g 1 amod(f) (25) (26) (27)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 19 application information minimum load resistance care must be taken not to load down the output of the error amplifier with the feedback resistor, r2, that is too small. the error amplifier has a finite output source and sink current which must be considered when sizing r2. too small a value does not allow the output to swing over its full range. r2 (min) v c(max) i source (min) 3.5 v 2ma 1750 calculating the boost an bp10 bypass capacitor the boost capacitance provides a local, low impedance source for the high-side driver. the boost capacitor should be a good quality, high-frequency capacitor. the size of the bypass capacitor depends on the total gate charge of the mosfet and the amount of droop allowed on the bypass capacitor. the boost capacitance is described in equation (29). c boost q g v (farads) the 10-v reference pin, bp10v provides energy for both the synchronous mosfet and the high-side mosfet via the boost capacitor. neglecting any efficiency pen alty, the bp10v capacitance is described in equation (30). c bp10 q ghs q gsr v (farads) dv/dt induced turn-on mosfets are susceptible to dv/dt turn-on particularly in high-voltage (v ds ) applications. the turn-on is caused by the capacitor divider that is formed by c gd and c gs . high dv/dt conditions and drain-to-source voltage, on the mosfet causes current flow through c gd and causes the gate-to-source voltage to rise. if the gate-to-source voltage rises above the mosfet threshold voltage, the mosfet turns on, resulting in large shoot-through currents. therefore, the sr mosfet should be chosen so that the c gd capacitance is smaller than the c gs capacitance. (28) (29) (30)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 20 a pplication information high side mosfet power dissipation the power dissipated in the external high-side mosfet is comprised of conduction and switching losses. the conduction losses are a function of the i rms current through the mosfet and the r ds(on) of the mosfet. the high-side mosfet conduction losses are defined by equation (31). p cond i rms 2 r ds(on) 1 tc r t j 25 o c (watts) where: tc r is the temperature coefficient of the mosfet r ds(on) the tc r varies depending on mosfet technology and manufacturer, but typically ranges between .0035 ppm/ c and .010 ppm/ c. the i rms current for the high side mosfet is described in equation (32). i rms i out d a rms the switching losses for the high-side mosfet are descibed in equation (33). p sw(fsw) v in i out t sw f sw (watts) where: i o is the dc output current t sw is the switching rise time, typically < 20 ns f sw is the switching frequency typical switching waveforms are shown in figure 13. udg?0213 9 ? i anti?cross conduction synchronous rectifier on body diode conduction body diode conduction high side on i d1 i d2 i o sw 0 d 1?d figure 13. inductor current and sw node waveforms (31) (32) (33)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 21 application information the maximum allowable power dissipation in the mosfet is determined by equation (34). p t t j t a ja (watts) where: p t p cond p sw(fsw) (watts) and ja is the package thermal impedance. synchronous rectifier mosfet power dissipation the power dissipated in the synchronous rectifier mosfet is comprised of three components: r ds(on) conduction losses, body diode conduction losses, and reverse recovery losses. r ds(on ) conduction losses can be found using equation (29) and the rms current through the synchronous rectifier mosfet is described in equation (36). i rms i o 1 d amperes rms the body-diode conduction losses are due to forward conduction of the body diode during the anti?cross conduction delay time. the body diode conduction losses are described by equation (37). p dc 2 i o v f t delay f sw (watts) where: v f is the body diode forward voltage t delay is the delay time just before the sw node rises the 2-multiplier is used because the body diode conducts twice during each cycle (once on the rising edge and once on the falling edge). the reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a reverse blocking state. the reverse recovery losses are described in equation (38). p rr 0.5 q rr v in f sw (watts) where: q rr is the reverse recovery charge of the body diode the q rr is not always described in a mosfet?s data sheet, but may be obtained from the mosfet vendor. the total synchronous rectifier mosfet power dissipation is described in equation (39). p sr p dc p rr p cond (watts) (34) (35) (36) (37) (38) (39)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 22 application information tps4005x power dissipation the power dissipation in the tps4005x is largely dependent on the mosfet driver currents and the input voltage. the driver current is proportional to the total gate charge, qg, of the external mosfets. driver power (neglecting external gate resistance, refer to [2] can be calculated from equation (40). p d q g v dr f sw (watts driver) and the total power dissipation in the tps4005x, assuming the same mosfet is selected for both the high-side and synchronous rectifier is described in equation (41). p t 2 p d v dr i q v in (watts) or p t 2 q g f sw i q v in (watts) where: i q is the quiescent operating current (neglecting drivers) the maximum power capability of the device?s powerpad package is dependent on the layout as well as air flow. the thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air flow. ja 36.515 o c w the maximum allowable package power dissipation is related to ambient temperature by equation (44). p t t j t a ja (watts) substituting equation (37) into equation (35) and solving for f sw yields the maximum operating frequency for the tps4005x. the result is described in equation (45). f sw t j t a ja v dd i q 2 q g (hz) (40) (41) (42) (43) (44) (45)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 23 layout considerations the powerpad package the powerpad package provides low thermal impedance for heat removal from the device. the powerpad derives its name and low thermal impedance from the large bonding pad on the bottom of the device. for maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the package. the dimensions of this area depends on the size of the powerpad package. for a 16-pin tssop (pwp) package the area is 5 mm x 3.4 mm [3]. thermal vias connect this area to internal or external copper planes and should have a drill diameter suf ficiently small so that the via hole is effectively plugged when the barrel of the via is plated with copper. this plug is needed to prevent wicking the solder away from the interface between the package body and the solder-tinned area under the device during solder reflow. drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is plated at the surface of the board while simultaneously plating the barrel of the via. if the thermal vias are not plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a diameter equal to the via diameter of 0.1 mm minimum. this capping prevents the solder from being wicked through the thermal vias and potentially creating a solder void under the package. refer to powerpad thermally enhanced package [3] and the mechanical illustration at the end of this document for more information on the powerpad package. thermal pad 6,60 mm 6,20 mm 4,50 mm 4,30 mm 10 1 x: minimum powerpad = 1.8 mm x y: minimum powerpad = 1.4 mm y figure 14. powerpad dimensions mosfet packaging mosfet package selection depends on mosfet power dissipation and the projected operating conditions. in general, for a surface-mount applications, the dpak style package provides the lowest thermal impedance ( ja ) and, therefore, the highest power dissipation capability. however, the effectiveness of the dpak depends on proper layout and thermal management. the ja specified in the mosfet data sheet refers to a given copper area and thickness. in most cases, a lowest thermal impedance of 40 c/w requires one square inch of 2-ounce copper on a g?10/fr?4 board. lower thermal impedances can be achieved at the expense of board area. please refer to the selected mosfet?s data sheet for more information regarding proper mounting. grounding and circuit layout considerations the tps4005x provides separate signal ground (sgnd) and power ground (pgnd) pins. it is important that circuit grounds are properly separated. each ground should consist of a plane to minimize its impedance if possible. the high power noisy circuits such as the output, synchronous rectifier, mosfet driver decoupling capacitor (bp10), and the input capacitor should be connected to pgnd plane at the input capacitor. sensitive nodes such as the fb resistor divider, r t , and ilim should be connected to the sgnd plane. the sgnd plane should only make a single point connection to the pgnd plane. component placement should ensure that bypass capacitors (bp10 and bp5) are located as close as possible to their respective power and ground pins. also, sensitive circuits such as fb, rt and ilim should not be located near high dv/dt nodes such as hdrv, ldrv, boost, and the switch node (sw).
sgls219a ? november 2003 ? revised may 2008 www.ti.com 24 design example input voltage: 10 vdc to 24 vdc output voltage: 3.3 v 2% (3.234 v o 3.366) output current: 8 a (maximum, steady state), 10 a (surge, 10 ms duration, 10% duty cycle maximum) output ripple: 33 mv p-p at 8 a output load response: 0.3 v => 10% to 90% step load change, from 1 a to 7 a operating temperature: ?40 c to 85 c f sw =300 khz 1. calculate maximum and minimum duty cycles d min v o(min) v in(max) 3.324 24 0.135 d max v o(max) v in(min) 3.366 10 0.337 2. select switching frequency the switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit comparator. in order to maintain current limit capability, the on time of the upper mosfet, t on , must be greater than 300 ns (see electrical characteristics table). therefore v o(min) v in(max) t on t sw or 1 t sw f sw v o(min) v in(max) t on using 400 ns to provide margin, f sw 0.135 400 ns 337 khz since the oscillator can vary by 10%, decrease f sw , by 10% f sw 0.9 337 khz 303 khz and therefore choose a frequency of 300 khz. 3. select ? i in this case ? i is chosen so that the converter enters discontinuous mode at 20% of nominal load. i i o 2 0.2 8 2 0.2 3.2 a (46) (47) (48) (49) (50)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 25 design example 4. calculate the power losses power losses in the high-side mosfet (si7860dp) at 24-v in where switching losses dominate can be calculated from equation (51). i rms i o d 8 0.135 2.93 a substituting (32) into (31) yields p cond 2.93 2 0.008 ( 1 0.007 ( 150 25 )) 0.129 w and from equation (33), the switching losses can be determined. p sw(fsw) v in i o t sw f sw 24 v 8a 20 ns 300 khz 1.152 w the mosfet junction temperature can be found by substituting equation (35) into equation (34) t j p cond p sw ja t a ( 0.129 1.152 ) 40 85 136 o c 5. calculate synchronous rectifier losses the synchronous rectifier mosfet has two (2) loss components, conduction, and diode reverse recovery losses. the conduction losses are due to i rms losses as well as body diode conduction losses during the dead time associated with the anti-cross conduction delay. the i rms current through the synchronous rectifier from (36) i rms i o 1 d 8 1 0.135 7.44 a rms the synchronous mosfet conduction loss from (31) is: p cond i rms 2 r ds(on) 7.44 2 0.008 ( 1 0.007 ( 150 25 )) 0.83 w the body diode conduction loss from (37) is: p dc 2 i o v fd t delay f sw 2 8.0 a 0.8 v 100 ns 300 khz 0.384 the body diode reverse recovery loss from (38) is: p rr 0.5 q rr v in f sw 0.5 30 nc 24 v 300 khz 0.108 w the total power dissipated in the synchronous rectifier mosfet from (39) is: p sr p rr p cond p dc 0.108 0.83 0.384 1.322 w the junction temperature of the synchronous rectifier at 85 c is: t j p sr ja t a ( 1.322 ) 40 85 139 o c in typical applications, paralleling the synchronous rectifier mosfet with a schottky rectifier increases the overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode conduction and reverse recovery periods. (51) (52) (53) (54) (55) (56) (57) (58) (59) (60)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 26 design example 6. calculate the inductor value the inductor value is calculated from equation (6). l ( 24 3.3 v ) 3.3 v 24 v 3.2 a 300 khz 2.96 h a 2.9- h coev dxm1306?2r9 or 2.6- h panasonic etq?p6f2r9lfa can be used. 7. setting the switching frequency the clock frequency is set with a resistor (r t ) from the rt pin to ground. the value of r t can be found from equation (1), with f sw in khz. r t 1 f sw 17.82 10 6 23 k 164 k use 165 k 8. programming the ramp generator circuit the pwm ramp is programmed through a resistor (r kff ) from the kff pin to v in . the ramp generator also controls the input uvlo voltage. for an undervoltage level of 10 v, r kff can be calculated from (2) r kff v in(min) 3.5 58.14 r t 1340 k 71 k use 71.5 k 9. calculating the output capacitance (c o ) in this example the output capacitance is determined by the load response requirement of ? v = 0.3 v for a 1 a to 8 a step load. c o can be calculated using (12) c o 2.9 ( 8a ) 2 ( 1a ) 2 ( 3.3 ) 2 ( 3.0 ) 2 97 f using (7) we can calculate the esr required to meet the output ripple requirements. 33 mv 3.2 a esr 1 8 73 f 300 khz esr 10.3 m 3.33 m 6.97 m for this design example two (2) panasonic sp eefueoj1b1r capacitors, (6.3 v, 180 f, 12 m ?) are used. 10. calculate the soft-start capacitor (c ss ) this design requires a soft?start time (t start ) of 1 ms. c ss can be calculated on (14) c ss 2.3 a 0.7 v 1ms 3.29 nf 3300 pf (61) (62) (63) (64) (65) (66) (67)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 27 design example 11. calculate the current limit resistor (r ilim ) the current limit set point depends on t start , v o ,c o and i load at start-up as shown in equation (15). for this design, i lim 360 f 3.3 v 1ms 8.0 a 9.2 a for this design, set i lim for 11.0 a dc minimum. from equation (16), with i oc equal to the dc output surge current plus one-half the ripple current of 3.2 a and r ds(on) is increased 30% (1.3 * 0.008) to allow for mosfet heating. r ilim 12.6 a 0.0104 1.12 10 a ( 0.075) 10 a 11.7 k 7.5 k 4.2 k 4.22 k 12. calculate loop compensation values calculate the dc modulator gain (a mod ) from equation (19) a mod 10 2 5.0 a mod(db) 20 log ( 5 ) 14 db calculate the output filter l-c o poles and c o esr zeros from (21) and (22) f lc 1 2 l c o 1 2 2.9 h 360 f 4.93 khz and f z 1 2 esr c o 1 2 0.006 360 f 73.7 khz select the close-loop 0 db crossover frequency, f c . for this example f c = 20 khz. select the double zero location for the t ype iii compensation network at the output filter double pole at 4.93khz. select the double pole location for the type iii compensation network at the output capacitor esr zero at 73.7 khz. the amplifier gain at the crossover frequency of 20 khz is determined by the reciprocal of the modulator gain amod at the crossover frequency from equation (27). a mod(f) a mod f lc f c 2 5 4.93 khz 20 khz 2 0.304 and also from equation (27). g 1 a mod(f) 1 0.304 3.29 choose r1 = 100 k ? (68) (69) (70) (71) (72) (73) (74)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 28 design example the poles and zeros for a type iii network are described in equations (25) and (26). f z2 1 2 r1 c3 c3 1 2 100 k 4.93 khz 323 pf, choose 330 pf f p2 1 2 r3 c3 r3 1 2 330 pf 73.3 khz 6.55 k , choose 6.49 k f c 1 2 r1 c2 g c2 1 2 100 k 3.29 20 khz 24.2 pf, choose 22 pf f p1 1 2 r2 c2 r2 1 2 22 pf 73.3 khz 98.2 k , choose 97.6 k f z1 1 2 r2 c1 c1 1 2 97.6 k 4.93 khz 331 pf, choose 330 pf calculate the value of r bias from equation (23) with r1 = 100 k ? . r bias 0.7 v r1 v o 0.7 v 0.7 v 100k 3.3 v 0.7 v 26.9 k , choose 26.7 k calculating the boost and bp10v bypass capacitance the size of the bypass capacitor depends on the total gate charge of the mosfet being used and the amount of droop allowed on the bypass cap. the boost capacitance for the si7860dp, allowing for a 0.5 voltage droop on the boost pin from equation (29) is: c boost q g v 18 nc 0.5 v 36 nf and the bp10v capacitance from (30) is c bp(10 v) q ghs q gsr v 2 q g v 36 nc 0.5 v 72 nf for this application, a 0.1- f capacitor is used for the boost bypass capacitor and a 1.0- f capacitor is used for the bp10v bypass. figure 15 shows component selection for the 10-v to 24-v to 3.3-v at 8 a dc-to-dc converter specified in the design example. for an 8-v input application, it may be necessary to add a schottky diode from bp10 to boost to get sufficient gate drive for the upper mosfet. as seen in figure 7, the bp10 output is about 6 v with the input at 8 v so the upper mosfet gate drive may be less than 5 v. references 1. balogh, laszlo, design and application guide for high speed mosfet gate drive circuits , texas instruments/unitrode corporation, power supply design seminar, sem?1400 topic 2. 2. powerpad thermally enhanced package texas instruments, semiconductor group, technical brief: ti literature no. slma002 (75) (76) (77) (78) (79) (80) (81) (82)
sgls219a ? november 2003 ? revised may 2008 www.ti.com 29 1 2 3 4 16 15 14 13 ilim vin boost hdrv kff rt bp5 sync tps40050pwp tps40051pwp 5 6 7 8 12 11 10 9 sw bp10 ldrv pgnd sgnd ss vfb comp + ? + ? si7860 pwp 470 pf 1n4150 optional hysteresis for uvlo d2 330 f 330 f r kff 71.5 k ? 4.22 k ? 100 pf 0.1 f 22 f 50 v 22 f 50 v r3 6.49 k ? r1 100 k ? 180 f 180 f v out v in r bias 26.7 k ? 1.0 f r2 97.6 k ? 1.0 f 499 k ? udg?02190 c3 330 pf r sw 3.3 ? 1.0 k ? c ss 3300 pf c1 330 pf c2 22 pf r t 165 k ? 2.9 h 1.0 f figure 15. 24-v to 3.3-v at 8-a dc-to-dc converter design example
package option addendum www.ti.com 11-mar-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps40050qpwprq1 active htssop pwp 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 40050q1 tps40051qpwprq1 active htssop pwp 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 40051q1 tps40053qpwprq1 obsolete htssop pwp 16 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and
package option addendum www.ti.com 11-mar-2015 addendum-page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tps40050-q1, tps40051-q1, TPS40053-Q1 : ? catalog: tps40050 , tps40051 , tps40053 note: qualified version definitions: ? catalog - ti's standard catalog product

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